A three-dimensional large scale integrated circuit (LSI) semiconductor device in which a plurality of LSI chips (or semiconductor bodies) are stacked has been proposed. For example, one type of three-dimensional LSI is a hybrid memory cube (HMC) configured by stacking a plurality of DRAM chips.
One technology for stacking a plurality of LSI chips in a three-dimensional LSI is a through silicon via (TSV), which is a via wire (or via) passing through a silicon substrate. By forming a TSV in the silicon substrate, it is possible to directly connect together a plurality of stacked LSI chips.
In order to connect chips together by TSV, micro-bump pads are provided on the front surface and rear surface of the chips. The micro-bump pads on the rear surface side of the chip are connected to the TSV, and the TSV are connected to the circuits inside the chip. Therefore, by connecting the micro-bump pads on the rear surface side of one of the two chips with the micro-bump pads on the front surface side of the other of the two chips, via the micro-bumps, the chips can be connected directly together. The micro-bumps are smaller than C4 bumps made by a controlled collapse chip connection (C4) method. Therefore, the size of the micro-bump pads is smaller than the C4 bump pads.
A three-dimensional LSI using TSV is described in Japanese Laid-open Patent Publication No. 2012-255704 and Japanese National Publication of International Patent Application No. 2013-531891.